Current microprocessors employ an instruction cache (I-cache) to increase the performance of a system. An I-cache stores the most frequently executed instructions and provides the processor easy and fast access to these instructions. While increasing the performance of the system, I-cache architectures also create security weaknesses.
One security weakness in conventional implementations of I-cache structures involves shared I-cache units in simultaneous multithreaded (SMT) and/or multi-core systems, wherein I-cache units are shared between different logical or physical microprocessors (FIG. 1). If more than two processes are executing simultaneously on the same system and if the I-cache is shared between these processes, then a malicious process can indirectly observe the execution of security critical applications and discover confidential values used therein by analyzing I-cache modifications.
Another security weakness in conventional implementations of I-cache structures involves ability of a malicious process to evict the entries of cryptographic processes from the I-cache, which enables an adversary to spy on the execution of cryptographic operations.